The present invention relates to A/D converters (analog-to-digital converters), and in particular how to enable background calibration of such converters.
The maximum achievable accuracy-speed performance of any A/D-converter is limited by non-ideal effects associated with its building blocks. Typically, the performance is limited by settling time, finite amplifier gain and/or analog component mismatch. When designing high-speed, high-accuracy A/D converters, these limitations impose very stringent demands on the building blocks, leading to prolonged design time. They also require the use of manufacturing processes that are optimized for component matching and performance, thus increasing the manufacturing cost.
Many non-ideal effects can be compensated for by using calibration. The problem is that the efficiency of the calibration may be degraded by drift and ageing. Therefore it is desirable to be able to continuously calibrate the A/D converter during normal operation.
One of the more popular approaches to background calibration is to use the xe2x80x9cskip-and-fillxe2x80x9d approach [1]-[2]. During normal operation, every kth sample is skipped, and the hardware is reconfigured to perform a calibration operation. The gap representing the skipped sample is filled by interpolation by using a number of adjacent samples. The problem with these solutions is that interpolation can only predict the skipped sample accurately when the input signal has a limited bandwidth. If the input signal is completely random, or if it can have any frequency over the entire Nyquist bandwidth, any guess is as good as the interpolated value. In the implementation described in [2], the performance is seen to degrade significantly for input frequencies above ⅔ of the Nyquist frequency (fs/2). So, even with as much as 44 taps interpolation (22 samples before, and 22 samples after the gap), it is not possible to accurately track more than ⅔ of the Nyquist bandwidth. This is in accordance with the theory described in [1]. Such a high-order interpolation requires a significant amount of digital hardware, and a long output delay (latency).
Another method to create a calibration time-slot is found in [3], where an input sample queue is formed by a cascade of sample-and-hold circuits. By emptying the queue slightly faster than it is filled, a calibration time-slot is occasionally available. The drawback with the xe2x80x9cinput-queuexe2x80x9d method is that each extra sample-and-hold stage adds distortion and noise. Therefore this approach is not optimal for high-speed, high-resolution A/D converters.
A background calibration approach applicable to pipelined A/D converters is proposed in [4]. The principle is to temporarily remove the pipeline stage to be calibrated from the signal path, and replace it with a substitute extra pipeline stage. Calibration of the disconnected pipeline-stage is then performed outside the pipeline. This xe2x80x9chardware-substitutionxe2x80x9d method is limited in several ways:
1. Its application is limited to pipeline A/D converters, or at least to A/D converter architectures having a cascade of identical stages.
2. The calibration is done outside of the conversion signal path, which means that the stage under calibration is not seeing the same environment as during normal operation. This may lead to incomplete calibration.
3. The conversion signal path is always filled with conversion samples. Thus it is not possible to insert a calibration value in the pipeline, or switch the pipeline to calibration mode. This effectively rules out the use of a large range of high-performance digital calibration schemes, such as the ones described in [5]-[6].
Another class of A/D converters is described in [7]. These A/D converters use several identical low sample rate A/D conversion units in parallel to build a high sample rate A/D converter. The units sample the analog signal in a cyclical manner. Calibration of one unit may be performed when another unit is sampling. Thus, no interpolation is necessary. However, this type of parallel converter is also very complex and expensive.
An object of the present invention is to enable the use of a wide range of calibration methods, without the inherent signal-bandwidth limitations imposed by the interpolation used in prior-art xe2x80x9cskip-and-fillxe2x80x9d methods and at a lower cost than the parallel A/D converter solution.
This object is achieved in accordance with the attached claims.
Briefly, the present invention provides a low performance auxiliary A/D converter that occasionally replaces the regular A/D converter for calibration purposes. Here the term xe2x80x9clow performancexe2x80x9d means lower performance than the regular A/D converter. The fact that the auxiliary A/D converter only has to be used occasionally (low sampling rate) means that the requirements on the auxiliary A/D converter are lower. Thus, parameters such as bit resolution and settling/conversion time are less critical.